The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for providing improved placement of structured nets, e.g., high fanout nets and high fanout paths, in integrated circuit design, synthesis, verification, and fabrication.
Physical synthesis is the process in which a semiconductor device is taken from the list of components and connections, referred to as a netlist, to a geometrical layout of the device. Placement processes are critical processes in physical synthesis. The task of placement processes is to determine the overall locations of standard cells or modules in a semiconductor device design. Each cell/module is a set of electrical components with input and output pins interconnected by a set of nets. After the placement process is completed, the resulting semiconductor device design is typically optimized with respect to device timing.
Transformations may be performed during the placement process to reduce the weighted total wire length (WTWL) of the device. During each transformation, the cells/modules of the design may be recursively moved according to transform guidelines. The placement of the cells after these moves may or may not be legal according to a set of design rules and thus, the transformation may also need to legalize the placement by moving cells/modules to ensure that the transformed placement meets the requirements, or does not result in a violation of, the design placement rules. After legalization, the transformation has produced a new legal placement of the cells/modules.
The placement operation is broken down into three steps: (a) global placement, (b) legalization, and (c) detailed placement. With global placement, an intial placement solution is generated for in the manner summarized above using transformations. Global placement ignores the non-overlapping constraint among the cells/modules. In this stage, the placement process has a global view of the entire netlist and optimizes the design objective(s) to obtain approximate locations for the cells/modules.
Once the initial placement solution is obtained through global placement operations, legalization ensures that the initial placement solution does not violate established placement rules and if the initial placement solution does violate any of these placement rules, the placement solution is adjusted to ensure legal placement of the cells/modules. With legalization, the overlap among the modules are resolved to obtain a “legal” overlap-free placement, for example.
Finally, detailed placement is performed to further optimize the design objective in a local region. For example, detailed placement may perform transformations of the placement solution of the semiconductor device design to convert cell/module placement from one location to another location within the device. These transformations may not only modify the placement of cells/modules but may also insert new cells/modules or change the size of existing cells/modules. The transformations are generally an iterative process performing a series of incremental move steps. Placement changes during detailed placement may again result in overlaps between cells/modules. Thus, legalization operations may further be performed during detailed placement so as to remove the cell/module overlaps. Legalization operations for detailed placement are designed to minimize the disturbance to the original placement by taking a legally placed netlist and changing locations of cells/modules while still maintaining legality.
Current microprocessor trends integrate custom designs with random logic macros (RLMs) to generate very large integrated circuit designs. In some cases, entire microprocessor units are designed using an automated synthesis flow that integrates these traditional custom designs and RLMs. This type of merged synthesis is often referred to as Large Block Synthesis (LBS). The LBS blocks, i.e. sets of cells/modules, require handling dataflow designs differently than traditional RLMs because RLM logic placement optimizes the locations of cells/modules for low fanout nets, e.g., 1 to 4 pin connectors. RLM logic placement optimizes for low fanout nets because RLMs typically have very few, if any, high fanout nets (HFNs), e.g., one or more hundreds of pin connectors. In dataflow design, however, HFN placement significantly impacts overall timing closure. Thus, RLM placement, which has been traditionally used for LBS, does not provide an optimum placement of logic blocks having high fanout nets.